1. Field of the Invention
The present invention relates to a signal transfer circuit.
Priority is claimed on Japanese Patent Application No. 2011-250684, filed Nov. 16, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
In many system large-scale integrations (LSIs) mounted on image processing apparatuses such as a still-image camera, a moving-image camera, a medical endoscope camera, and an industrial endoscope camera, a plurality of embedded processing blocks (hereinafter referred to as “bus masters”) share one connected dynamic random access memory (DRAM). In the system LSIs as described above, each of the plurality of embedded bus masters accesses the DRAM using direct memory access (DMA). In addition, the system LSI includes an arbiter that arbitrates an access request to the DRAM issued from each of a plurality of embedded bus masters. The arbiter controls actual access to the DRAM while appropriately arbitrating the access request to the DRAM issued from each bus master.
In the system LSI as described above, a protocol related to timings of signals input and output between the arbiter and the bus master is predetermined. In this protocol, the timing of a control signal between the arbiter and the bus master such as the access request to the DRAM output from the bus master to the arbiter or the access permission to the DRAM output from the arbiter to the bus master is set. In addition, in this protocol, the timing of data between the arbiter and the bus master, such as data written to the DRAM that is output from the bus master to the arbiter, and data read from the DRAM that is output from the arbiter to the bus master, is defined.
FIGS. 10A and 10B are diagrams illustrating examples of configurations and control timings of an arbiter and bus masters in a system LSI in accordance with the related art. In FIG. 10A, an example of connections between the arbiter and the bus masters in the system LSI in accordance with the related art is illustrated. In the system LSI in accordance with the related art, for example, as illustrated in FIG. 10A, a plurality of bus masters 92 to 94 are connected to an arbiter 91 and share one DRAM 90. Although a plurality of signal lines only connected between the arbiter 91 and the bus master 92 are illustrated in FIG. 10A, a plurality of signal lines are also similarly connected between the arbiter 91 and the bus masters 93 and 94.
In FIG. 10B, an example of a timing chart according to a protocol in the system LSI in accordance with the related art is illustrated. In FIG. 10B, a timing chart of signals when data is written from the bus master to the DRAM is illustrated. In the following description, the case in which the bus master 92 writes data to the DRAM 90 will be described.
If a request (REQ) signal indicating an access request to the DRAM 90 from each of the bus masters 92 to 94 illustrated in FIG. 10A to the arbiter 91 is issued (output), the arbiter 91 selects one bus master (for example, the bus master 92) according to a predetermined arbitration algorithm. The arbiter 91 returns (outputs) an acknowledge (AEN) signal indicating the acceptance of the access request, that is, the permission of the access request, to the selected bus master (for example, the bus master 92).
The bus master 92 whose access request has been accepted, that is, the bus master 92 to which the acknowledge (AEN) signal has been input, stops the issuance of the request (REQ) signal in the same clock cycle when the next access request to the DRAM 90 is not continuously issued.
In addition, the arbiter 91 issues (outputs) a data enable (DEN) signal indicating a period in which writing of data to the DRAM 90 is valid to the bus master 92 whose access request has been accepted at a timing at which data access to the DRAM 90 is possible. If the data enable (DEN) signal is input, the bus master 92 sequentially outputs write data (WDATA), which is data to be written to the DRAM 90, from the same clock cycle. In FIG. 10B, the case in which write data (WDATA) of four bursts is sequentially output is illustrated.
When the bus master reads data from the DRAM, read data (RDATA), which is data read from the DRAM output from the arbiter at the same timing as write data (WDATA) illustrated in FIG. 10B is received.
As described above, each bus master accesses the DRAM (writes data to the DRAM or reads data from the DRAM) via the arbiter by performing access at the timing of a predetermined protocol between the arbiter and the bus master (for example, see Japanese Unexamined Patent Application, First Publication No. 2006-39672).
However, in the protocol as described above, there are paths in which timing for signals that are input and output between the arbiter and the bus master is strict. FIGS. 11A and 11B are diagrams illustrating an example of a path in which timing is strict in the system LSI in accordance with the related art. In FIG. 11A, an example of control timings in which timing when data is written from the bus master to the DRAM is strict is illustrated. In FIG. 11B, a path of a signal line in which timing is strict in an example of a connection between the arbiter and the bus master in the system LSI in accordance with the related art is illustrated. In FIG. 11B, the case in which the bus master 92 writes data to the DRAM 90 and the bus master 93 reads data from the DRAM 90 is illustrated.
As illustrated in FIG. 11A, when the bus master continuously issues an access request to the DRAM 90, the bus master should perform (control) issuance stop and re-issuance of a request (REQ) signal corresponding to an acknowledge (AEN) signal input from the arbiter 91 within one clock cycle (see timing A of FIG. 11A). In addition, even when each bus master outputs write data (WDATA) corresponding to a data enable (DEN) signal input from the arbiter 91 or even when read data (RDATA) input along with the data enable (DEN) signal is received, it is necessary to access all of the data within one clock cycle (see timing B of FIG. 11A).
In this case, a path indicated by a heavy line in FIG. 11B serves as a path in which timing is strict. More specifically, when the bus master 92 continuously issues an access request to the DRAM 90, the acknowledge (AEN) signal input from an arbitration circuit 911 of the arbiter 91 is first input to a request generation circuit 921 (a request generation circuit 931 in the bus master 93). If the acknowledge (AEN) signal is input, the request generation circuit 921 (or the request generation circuit 931) determines whether to stop the issuance of the request (REQ) signal or whether to continuously issue the request (REQ) signal. When the issuance of the request (REQ) signal is determined to be stopped, the request generation circuit 921 (or the request generation circuit 931) initializes (resets) a flip-flop 922 (a flip-flop 932 in the bus master 93). In addition, when the request (REQ) signal is determined to be continuously issued, the request generation circuit 921 (or the request generation circuit 931) inputs the request (REQ) signal to the flip-flop 922 (or the flip-flop 932). Because the determination by the request generation circuit 921 (or the request generation circuit 931) and control for the flip-flop 922 (or the flip-flop 932) should be performed during a clock cycle in which the acknowledge (AEN) signal has been input, that is, because the determination result should be reflected in the next clock cycle, timing becomes severe.
In addition, when the bus master 92 outputs the write data (WDATA), the data enable (DEN) signal input from the arbitration circuit 911 within the arbiter 91 is first input to the data control circuit 923. The data control circuit 923 outputs the write data (WDATA) to be initially output to the arbiter 91 to a flip-flop 924 based on the input data enable (DEN) signal. The data control circuit 923 needs to output the initial write data (WDATA) to the flip-flop 924 until the next clock cycle of the flip-flop 924. Thereafter, the data control circuit 923 sequentially outputs the next write data (WDATA) to the flip-flop 924 for every clock cycle. In FIG. 11A, the case in which four-burst write data (WDATA) is output twice in continuity is illustrated.
In addition, when the bus master 93 receives read data (RDATA), a data enable (DEN) signal input from the arbitration circuit 911 within the arbiter 91 is first input to a data latch control circuit 933. The data latch control circuit 933 outputs a data latch signal for receiving the read data (RDATA) initially output from the arbiter 91 to the flip-flop 934 based on the input data enable (DEN) signal. The data latch control circuit 933 needs to output an initial data latch signal to the flip-flop 934 before the next clock cycle of the flip-flop 934. Thereafter, the data latch control circuit 933 sequentially outputs a data latch signal for receiving the next read data (RDATA) to the flip-flop 934.
As described above, there is a path in which timing is strict according to a limitation of the protocol in the system LSI in accordance with the related art. The strict timing of the path becomes stricter if a distance between a position in which the arbiter 91 is disposed within the system LSI and a position in which each bus master is disposed increases. Thus, it is difficult to increase the number of embedded bus masters for a high-performance system LSI in the system LSI in accordance with the related art. This is because the distance between the position in which the arbiter 91 is disposed within the system LSI and the position in which each bus master is disposed is likely to be further increased by increasing the number of bus masters to be embedded in the system LSI.
If the layout positions of the arbiter and the bus master are away from each other, a wiring length of a signal to be input and output between the arbiter and the bus master becomes long and a delay time of wiring increases. If the delay time of wiring increases, a time until the acknowledge (AEN) signal or the data enable (DEN) signal output from the arbitration circuit 911 within the arbiter 91 is input to each bus master becomes long. Thereby, there is a problem in that a time available for control or a data output that is necessary to be performed before the next clock cycle within the bus master becomes short and the control or the data output does not end before the next clock cycle, that is, the protocol is not conformed.
In addition, a circuit scale of the arbitration circuit 911 within the arbiter 91 also increases by increasing the number of bus masters embedded in the system LSI. Thereby, the number of circuit stages (the number of logical stages) through which each signal passes also increases. Thus, an output of the acknowledge (AEN) signal or the data enable (DEN) signal from the arbitration circuit 911 may also be delayed.
In addition, it is difficult to speed up an operation clock for a high-performance system LSI in the system LSI in accordance with the related art. This is because a period of one clock cycle is shortened by speeding up the operation clock of the system LSI.
If the period of one clock cycle is shortened, the time available for the control or the data output that is necessary to be performed before the next clock cycle within the bus master is also shortened. Thus, there is a problem in that it may be impossible to speed up an operation clock to a certain extent or more to keep the protocol when a delay time of a signal by the number of logical stages of the request generation circuit 921 (or the request generation circuit 931), the data control circuit 923, or the data latch control circuit 933 is considered.
The acknowledge (AEN) signal or the data enable (DEN) signal output from the arbitration circuit 911 within the arbiter 91 is also temporarily latched in the flip-flop, so that a time available for the control or data output necessary to be performed within one clock cycle may be secured.
FIGS. 12A and 12B are diagrams illustrating an example of a configuration and control timings of a bus master that latches a signal output from an arbiter in the system LSI in accordance with the related art. In FIG. 12A, an example of a connection between the arbiter and the bus master that latches the signal output from the arbiter in the system LSI in accordance with the related art is illustrated. FIG. 12A illustrates the configuration of the bus master in which a flip-flop 925 that latches the acknowledge (AEN) signal output from the arbitration circuit 911 within the arbiter 91 and a flip-flop 926 that latches the data enable (DEN) signal output from the arbitration circuit 911 within the arbiter 91 are added to the bus master 92 illustrated in FIG. 11B.
In FIG. 12B, an example of a timing chart according to the protocol in the system LSI in accordance with the related art is illustrated. In FIG. 12B, a timing chart of signals when data is written from the bus master 92 illustrated in FIG. 12A to the DRAM is illustrated. In the following description, it is described that the next access request to the DRAM 90 is not continuously issued when the bus master 92 writes data to the DRAM 90.
If the request (REQ) signal representing the access request to the DRAM 90 from the bus master 92 to the arbiter 91 is issued (output) as illustrated in FIG. 12A, the arbiter 91 selects the bus master 92 according to a predetermined arbitration algorithm and returns (outputs) the acknowledge (AEN) signal. The bus master 92 temporarily latches the input acknowledge (AEN) signal in the flip-flop 925 and outputs the latched acknowledge (AEN_d) signal to the request generation circuit 921. The request generation circuit 921 stops the issuance of the request (REQ) signal by initializing the flip-flop 922 based on the acknowledge (AEN_d) signal temporarily latched by the flip-flop 925.
Thereby, the request (REQ) signal input to the arbiter 91 is stopped as illustrated in FIG. 12B. However, because the issuance of the request (REQ) signal is stopped based on the acknowledge (AEN_d) signal temporarily latched by the flip-flop 925, a timing delayed by a period C of FIG. 12B is provided. Thus, the arbiter 91 falsely recognizes that the access request to the DRAM 90 has been continuously issued from the bus master 92 during the period C.
In addition, the arbiter 91 issues (outputs) the data enable (DEN) signal to the bus master 92 at the timing at which data access to the DRAM 90 is possible. The bus master 92 temporarily latches the input data enable (DEN) signal in the flip-flop 926, and outputs the latched data enable (DEN_d) signal to the data control circuit 923. The data control circuit 923 outputs write data (WDATA) initially output to the arbiter 91 to the flip-flop 924 based on the data enable (DEN_d) signal temporarily latched by the flip-flop 926. The data control circuit 923 outputs the initial write data (WDATA) to the flip-flop 924 before the next clock cycle of the flip-flop 924.
Thereby, as illustrated in FIG. 12B, the write data (WDATA) is input from the bus master 92 to the arbiter 91. However, because the output of the write data (WDATA) to the arbiter 91 is performed based on the data enable (DEN_d) signal temporarily latched by the flip-flop 926, its timing is later than that of the data enable (DEN) signal output by the arbiter 91 as illustrated in period D of FIG. 12B. Thus, the arbiter 91 writes data to the DRAM 90 before the initial write data (WDATA) is input from the bus master 92 at the beginning of period D. In addition, at the end of period D, the arbiter 91 does not write the last (fourth) write data (WDATA) input from the bus master 92 to the DRAM 90.
When the bus master reads data from the DRAM, read data (RDATA) is input to the bus master at the same timing as that of the write data (WDATA) illustrated in FIG. 10B or 11A. At this time, the timing of the data latch signal based on the data enable (DEN_d) signal temporarily latched by the flip-flop is later than that of the data enable (DEN) signal output by the arbiter 91. Thus, it may be impossible for the bus master (for example, the bus master 93) receiving the read data (RDATA) to receive the initial read data (RDATA) output from the arbiter 91. In addition, the bus master receives data after the last read data (RDATA) output from the arbiter 91.
As described above, in a method of securing a time available for control or a data output necessary to be performed within one clock cycle by simply temporarily latching the acknowledge (AEN) signal or the data enable (DEN) signal output from the arbiter in a flip-flop, it may be impossible to access the DRAM in a state in which the above-described protocol predetermined between the arbiter and the bus master has been kept.